22. January 2022

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Cadence Design Systems announced a new DRAM verification solution, allowing customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications. Using the full DRAM verification solution, which delivers up to 10X increased verification throughput, customers can perform IP-to-SoC-level verification of advanced designs with multiple DDR interfaces. Modern SoC designs leverage advanced memory technologies, such as LPDDR5x, DDR5, HBM3 and GDDR6, which require rigorous verification at the PHY and IP … More

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